1. Field of the Invention
Generally, the present disclosure relates to microstructures, such as advanced integrated circuits, and, more particularly, to conductive structures, such as copper-based metallization layers, comprising metal lines and vias.
2. Description of the Related Art
In the fabrication of modern microstructures, such as integrated circuits, there is a continuous drive to steadily reduce the feature sizes of microstructure elements, thereby enhancing the functionality of these structures. For instance, in modern integrated circuits, minimum feature sizes, such as the channel length of field effect transistors, have reached the deep sub-micron range, thereby increasing performance of these circuits in terms of speed and/or power consumption and/or diversity of functions. As the size of individual circuit elements is reduced with every new circuit generation, thereby improving, for example, the switching speed of the transistor elements, the available floor space for interconnect lines electrically connecting the individual circuit elements is also decreased. Consequently, the dimensions of these interconnect lines are also reduced to compensate for a reduced amount of available floor space and for an increased number of circuit elements provided per unit die area, as typically the number of interconnections required increases more rapidly than the number of circuit elements. Thus, usually, a plurality of stacked “wiring” layers, also referred to as metallization layers, is provided, wherein individual metal lines of one metallization layer are connected to individual metal lines of an overlying or underlying metallization layer by so-called vias. Despite the provision of a plurality of metallization layers, reduced dimensions of the interconnect lines are necessary to comply with the enormous complexity of, for instance, modern CPUs, memory chips, ASICs (application specific ICs) and the like.
Advanced integrated circuits, including transistor elements having a critical dimension of 0.05 μm and even less, may, therefore, typically be operated at significantly increased current densities of up to several kA per cm2 in the individual interconnect structures, despite the provision of a relatively large number of metallization layers, owing to the significant number of circuit elements per unit area. Consequently, well-established materials, such as aluminum, are being replaced by copper and copper alloys, i.e., materials with significantly lower electrical resistivity and improved resistance to electromigration, even at considerably higher current densities, compared to aluminum. The introduction of copper into the fabrication of microstructures and integrated circuits comes along with a plurality of severe problems residing in copper's characteristic to readily diffuse in silicon dioxide and a plurality of low-k dielectric materials, which are typically used in combination with copper in order to reduce the parasitic capacitance within complex metallization layers.
Another characteristic of copper significantly distinguishing it from aluminum is the fact that copper may not be readily deposited in larger amounts by chemical and physical vapor deposition techniques and it does not form volatile etch byproducts when exposed to currently established etch processes, thereby requiring a process strategy that is commonly referred to as the damascene or inlaid technique. In the damascene process, first a dielectric layer is formed which is then patterned to include trenches and/or vias which are subsequently filled with copper, wherein, prior to filling in the copper, a conductive barrier layer is formed on sidewalls of the trenches and vias. The deposition of the bulk copper material into the trenches and vias is usually accomplished by wet chemical deposition processes, such as electroplating and electroless plating, thereby requiring the reliable filling of vias with an aspect ratio of 5 and more with a diameter of 0.3 μm or even less, in combination with trenches having a width ranging from 0.1 μm to several μm. Electrochemical deposition processes for copper are well established in the field of electronic circuit board fabrication. However, for the dimensions of the metal regions in semiconductor devices, the void-free filling of high aspect ratio vias is an extremely complex and challenging task, wherein the characteristics of the finally obtained copper-based interconnect structure significantly depend on process parameters, materials and geometry of the structure of interest. Since the basic geometry of interconnect structures is substantially determined by the design requirements and may, therefore, not be significantly altered for a given microstructure, it is of great importance to estimate and control the impact of materials, such as conductive and non-conductive barrier layers, of the copper microstructure and their mutual interaction on the characteristics of the interconnect structure so as to insure both high yield and the required product reliability.
In addition, to achieve high production yield and superior reliability of the metallization system, it is also important to accomplish these goals on the basis of a high overall throughput of the manufacturing process under consideration. For instance, the so-called dual damascene process is frequently used, in which a via opening and a corresponding trench are filled in a common deposition sequence, thereby providing superior process efficiency.
In the damascene technique or inlaid technique, typically, the patterning of the via openings and the trenches may require sophisticated lithography techniques since the shrinkage of critical dimensions in the device layer, i.e., for transistors and other semiconductor circuit elements, may also require a corresponding adaptation of the critical dimensions of the vias and metal lines to be formed in the metallization system. In some well-established process techniques, a patterning regime may be used, which may commonly be referred to as “via first-trench last” approach, in which at least a portion of a via opening may be formed first on the basis of a specific etch mask and thereafter a corresponding trench mask may be provided in order to form a corresponding trench in the upper portion of the dielectric material, wherein, depending on the overall process strategy, during the trench etch process, the remaining portion of the via opening may also be completed, while, in other cases, the via opening may be provided such that it extends down to a bottom etch stop layer, which may then be opened after completing the trench etch process.
Consequently, a complex patterning regime including at least two critical lithography steps has to be used in order to provide appropriate etch masks for the via openings and the trenches. With shrinking critical dimensions of the circuit elements and thus also of the metal features to be provided in the metallization system of complex semiconductor devices, a precise definition of the lateral size of the trenches and via openings may become increasingly difficult since, for instance, the thickness of sophisticated resist materials has to be adapted to the sophisticated lithography conditions, which may typically restrict the effective etch resistivity of sophisticated resist materials. That is, significant progress has been made in optical lithography techniques, for instance by increasing numerical aperture and reducing the exposure wavelengths, for instance to approximately 193 nm in presently sophisticated lithography techniques, thereby also, however, reducing the depth of focus during the critical lithography processes. As a consequence of these developments, the characteristics of the resist materials also have to be adapted, thereby requiring a significant reduction of the usable layer thickness so that the resist material may not allow directly patterning any underlying low-k dielectric materials due to the reduced selectivity between the resist material and the dielectric material to be etched. Consequently, typical complex material systems, including hard mask materials and the like, have to be provided, in combination with superior process control regimes, in order to form critical features in the metallization system of the semiconductor device in accordance with the design requirements.
With reference to FIGS. 1a-1f, a typical configuration and manufacturing strategy for forming critical metallization layers of sophisticated semiconductor devices will now be described in more detail.
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 in an advanced manufacturing stage. As illustrated, the device 100 comprises a substrate 101 and a semiconductor layer 102, such as a silicon layer, in and above which a plurality of circuit elements 103, such as transistors, resistors, capacitors and the like, are provided. The circuit elements 103 typically comprise any components, such as gate electrode structures and the like, which may be formed on the basis of critical dimensions of 50 nm and less. For example, presently, complex semiconductor devices are under development in which a gate length of less than 30 nm is to be implemented when complex field effect transistors are considered. The circuit elements 103 are typically embedded in a dielectric material 111 of a contact level 110, wherein the dielectric material 111 may represent any appropriate material system, for instance based on silicon nitride, silicon dioxide and the like. A plurality of contact elements 112 provide electrical connection of the circuit elements 103 with a metallization system 120 of the device 100. In the manufacturing stage shown, metallization layers 130, 140 of the metallization system 120 are provided, wherein, as previously discussed, corresponding metal features may have to be adapted in size and packing density to the architecture and configuration of the circuit elements 103. For example, the metallization layer 130 may comprise any appropriate dielectric material 131, such as a low-k dielectric material and the like, in which are formed metal lines 132, which may appropriately connect to the contact elements 112. Thus, in densely packed device areas, the contact elements 112 and the metal lines 132 may have lateral dimensions, i.e., at least in the horizontal direction of FIG. 1a, that are comparable in magnitude to the critical lateral dimensions of the circuit elements 103. Similarly, metal lines 142L and vias 142V of the metallization layer 140 are embedded in a dielectric material 141, such as a low-k dielectric material, an ultra low-k (ULK) material and the like, and may appropriately connect to the metal lines 132.
In this respect, a low-k dielectric material is to be considered as a dielectric material having a dielectric constant of 3.0 or less, while typically a ULK material may be understood herein as a dielectric material having a dielectric constant of 2.7 and less. Furthermore, typically, an appropriate etch stop material 143, which may also act as a confinement or cap layer for the metal material in various metal features, may be provided in order to appropriately control the complex patterning process for forming at least the vias 142V in the metallization layer 140. The etch stop layer 143 may be provided in the form of a silicon material including nitrogen, carbon, oxygen and the like in order to provide superior etch stop capabilities, while not unduly increasing the overall permittivity of the metallization system 120. For example, a plurality of material compositions, also referred to as BLOK (bottom low-k) materials, have been developed with a dielectric constant of 4.0 and less, which may exhibit high etch resistivity with respect to any plasma assisted etch recipes used for patterning low-k dielectric materials, while also providing high copper diffusion blocking effects in order to suppress copper migration into sensitive device areas.
The semiconductor device 100 as illustrated in FIG. 1a may be formed on the basis of the following process strategies. The circuit elements 103 are typically formed by using sophisticated lithography techniques, deposition processes, implantation and etch techniques, wherein, however, many of the associated lithography and etch processes may be performed on the basis of a reduced layer thickness compared to the metallization system 120 and also on the basis of a superior device topography, thereby obtaining the desired critical dimensions, frequently without applying sophisticated hard mask and other sacrificial material systems. After completing the circuit elements 103, the contact level 110 may be formed by depositing the dielectric material or material system 111 and patterning the same in order to form openings, which may be subsequently filled with an appropriate conductive material, any excess portions thereof may be removed by chemical mechanical polishing (CMP) and the like, thereby providing the electrically insulated contact elements 112. The process of patterning the contact level 110, however, may contribute to a pronounced surface topography, thereby increasingly contributing to very sophisticated process conditions during the subsequent processing of the device 100. Thereafter, the metallization layer 130 may be formed by depositing the dielectric material 131 and patterning the same in order to fill in an appropriate conductive material, such as copper in combination with any appropriate barrier materials. After the removal of any excess material, the etch stop layer 143 may be deposited, followed by the dielectric material 141, which may also be patterned by sophisticated lithography techniques using any appropriate process strategy, such as a via-first approach and the like, wherein at least two critical lithography steps may have to be performed in order to define the lateral size and position of the vias 142V and of the metal lines 142ll. Typically, any such critical lithography processes and the subsequent patterning process for transferring the openings of the resist material finally into the underlying dielectric material may be performed on the basis of well-established control regimes, such as advanced process control regimes (APC), which are designed such that, based on a moderate amount of measurement data, a control of the process sequence may be achieved, in which the process result, i.e., the critical dimensions of the feature sizes under consideration, may be centered around the target value.
FIG. 1b schematically illustrates a corresponding process control regime for a process flow for forming the metal lines 142L and vias 142V (FIG. 1a). To this end, a manufacturing environment 150 may comprise a plurality of manufacturing and metrology tools in which a resist material may be patterned on the basis of photolithography and wherein finally trenches and via openings may be provided in a low-k dielectric material on the basis of any process strategies. For example, as shown, a first process module 151 may represent a portion of the manufacturing environment 150 in which a plurality of lithography tools and related process tools may be provided in order to form appropriate resist material layers on any substrates, such as the substrate 101. To this end, the module 151 may comprise spin-on process tools for forming one or more resist layers, pre-exposure bake tools, post-exposure bake tools, develop stations and the like. Moreover, the module 151 may comprise one or more lithography tools which may expose the resist material on the basis of respective lithography masks in order to transfer the mask pattern into the resist material. Moreover, a metrology module 152 may be provided, which may include any optical inspection techniques for determining the critical dimensions of the resist features after being processed in the lithography module 151. Hence, the metrology module 152 may provide respective measurement data from selected ones of the substrates 101 processed by the module 151 and may provide the measurement data to a control unit 155, which may, based on the desired CD target value, select an appropriate target value for one process parameter, which may sensitively influence the process result of the process module 151. For example, the control unit 155 may provide a target value for an exposure dose that is to be applied upon processing the substrate 101, wherein the unit 155 may determine the target value of the exposure dose such that, based on the measurement data obtained from the module 152, any substrates 101 to be processed in the module 151 are expected to substantially comply with the CD target value. To this end, the control unit 155 may have implemented therein any predictive model of, for instance, the exposure process in the module 151, which may correlate the measurement data from the module 152 with the desired CD target value. Moreover, the environment 150 may comprise a rework module 153, which may receive any substrates 101A which may not be within a valid range of the critical dimensions and which are thus expected to be outside of the specifications after finally transferring the critical dimensions of the resist layers into any lower-lying material in an etch module 156.
It should be appreciated that the lithography module 151 has a somewhat unique position in the whole manufacturing sequence for forming complex microstructure devices since the resist material may be efficiently removed without significantly affecting any underlying material layers, such as dielectric materials and the like, then by enabling a further application of resist material in order to reprocess the corresponding substrates in the lithography module 151. To this end, however, a plurality of additional process steps, such as cleaning processes and the like, may be required in the rework module 153, which may thus contribute to the overall production costs. Similarly, the processing of the substrates 101 in the lithography module 151 may represent one of the most cost-intensive process modules, so that undue increase of the number of substrates to be reworked may significantly affect overall throughput of the manufacturing environment 150.
FIG. 1c schematically illustrates a further portion of the manufacturing environment 150 in which a further metrology module 157 may be provided downstream of the etch module 156 in order to provide measurement data of the finally implemented critical dimensions, i.e., of any via openings and trenches formed in the low-k dielectric material of the metallization system of the substrate 101. It should be appreciated that the possibility of reworking any substrates after having been processed in the module 156 are very limited, since typically the removal of any invalidly patterned low-k dielectric materials may be difficult to achieve without significantly affecting any further device areas, such as lower-lying metallization layers and the like. The measurement data obtained from the module 157 may be supplied to a further control unit 158, which may provide appropriate target values for one or more etch steps for at least the etch step for patterning the low-k dielectric material under consideration. The control unit 158 may thus mainly strive to provide an etch result that is strongly correlated to the critical dimension obtained from a substrate after the lithography module 151, which may be forwarded to the etch module 156 if complying with the predefined valid range of critical dimensions determined by the metrology module 152 (FIG. 1b).
As a consequence, appropriate control regimes may be applied, for instance by using statistical process control techniques and the like, in combination with APC strategies in order to provide the final openings in the low-k dielectric material with actual lateral dimensions that may be distributed around the target values, wherein the spread of the distribution may indicate the quality of the overall process flow and thus also of the control mechanisms. It should be appreciated that a significant spread of the lateral dimensions of the corresponding openings may grossly affect the electrical performance of the resulting metallization system since, for instance, line resistance, parasitic capacitance and the like may be strongly correlated with the lateral dimensions of the resulting metal features.
FIG. 1d schematically illustrates a cross-sectional view of the semiconductor device 100 according to a process strategy in which via openings may be formed in the metallization layer 140 according to sophisticated lithography techniques. As illustrated, a hard mask material 104, such as a silicon dioxide material, may be provided on the low-k dielectric material 141, followed by an optical planarization material 105, which may typically be provided in the form of an organic material. Furthermore, a silicon-containing anti-reflective coating (ARC) layer 106 is formed on the planarization layer 105, followed by a resist mask 107, which may comprise a latent image in the form of exposed regions 107A, which may thus basically define the lateral size and position of via openings to be formed in the low-k dielectric material 141. As previously discussed, sophisticated lithography processes may require specifically adapted resist materials, which may no longer be applicable with a moderately large layer thickness, which, however, would be desirable in view of planarizing the overall surface topography of the device 100 prior to performing a critical lithography process and which would also be desirable in view of a high etch resistivity to pattern any underlying material layers. Moreover, in critical lithography processes, in particular using short wavelengths, such as 193 nm and less, superior ARC capabilities may be required wherein, for instance, a moderately high absorption is typically necessary in order to reduce the back reflection approximately one percent and less. Providing an ARC material on the basis of an organic material, which may be preferable in view of providing this material on the basis of spin-on techniques, however, may result in a low etch selectivity with respect to the resist material 107 so that frequently an additional ARC material may be used, such as the layer 106 comprising silicon as an inorganic component, thereby significantly increasing the etch resistivity with respect to a plurality of etch chemistries that are typically used for performing a patterning process based on a resist material. Consequently, on the basis of the exposed resist mask 107, i.e., after development of the resist material 107, the silicon-containing ARC layer 106 may be patterned and thereafter the underlying materials, i.e., the material 105 and finally the hard mask 104, may be patterned in order to transfer the mask openings 107A into the hard mask material 104.
As discussed above, prior to actually patterning the hard mask 104, the actual lateral dimensions of the openings 107A may be determined, for instance, in the metrology module 152 of FIG. 1b, in order to provide the desired measurement data for controlling the lithography process, as discussed above, and to determine whether or not the mask openings 107A have lateral dimensions within the predefined valid range. If dimensions of the mask openings 107A are not within the valid range, the device 100 may be subjected to a rework process which, however, may require the removal of the layers 105, 106 and 107, thereby resulting in a moderately complex rework process sequence.
FIG. 1e schematically illustrates the semiconductor device 100 in a corresponding manufacturing stage in which the mask openings 107A of the resist material 107 are transferred into the silicon-containing ARC layer, as indicated by 106A, which may thus have substantially the same lateral size as the openings 107A. During the corresponding etch process, which may be performed on the basis of a fluorine-based etch chemistry, a more or less pronounced amount of the resist layer 107 may be consumed, however, nevertheless enabling a reliable transfer of the pattern of the layer 107 into the ARC layer 106. Thereafter, the openings 106A may be transferred into the planarization material 105, for instance using an oxygen-based plasma ambient, wherein the resist material 107 may be consumed while, however, the silicon-containing ARC material 106 may provide efficient etch resistivity in order to etch through the material 105 and finally into the hard mask material 104.
FIG. 1f schematically illustrates the semiconductor device 100 during an etch process 108 that is configured to etch through low-k dielectric material 141 on the basis of the hard mask 104, which may comprise corresponding mask openings 104A that have been obtained on the basis of the openings 106A (FIG. 1e), as discussed above. During the etch process 108, process parameters, such as pressure, plasma power, temperature, and in particular the flow rates of any gas components, may be controlled so as to obtain a via opening 141V that substantially corresponds to the opening 104A of the hard mask 104. For example, low-k dielectric materials may be etched on the basis of C4F8 as a reactive gas component, possibly in combination with argon, nitrogen and the like, wherein the etch process 108 may be reliably stopped in and on the etch stop layer 143, which may then be opened by an additional etch step, for instance based on a reactive gas component comprising SF6 and oxygen and the like.
Consequently, a plurality of complex processes are typically associated with providing the via opening 141V, which may result in a significant spread of the resulting final critical dimensions of the via opening 141V with respect to a desired target value, since, for instance, independent control mechanisms may be implemented in the lithography process for forming the resist layer 107 (FIG. 1e) and in the etch process 108, as previously discussed with reference to FIGS. 1b and 1c, so that a plurality of process variabilities may not be appropriately taken account of in the control mechanism. Consequently, significant maintenance effort may have to be made, for instance in appropriately preparing the hardware resources, such as etch tools, lithography tools and the like, in order to avoid even subtle process fluctuations that may be caused by any variations of complex hardware tools. Furthermore, additional cleaning processes may be implemented in order to reduce overall process variations during the complex patterning process in order to avoid undue variation of the critical dimensions.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.